To manufacture electric circuits involves the formation of isolations between devices. Thus, to fabricate ICs, devices isolated from one another must first be formed in the silicon substrate. Establishing effective isolation in submicron ICs in the face of decreased isolation space is a complicated and challenging task. In ULSI, a tiny amount of leakage per device can induce significant power dissipation for the entire circuit.
Up to now, many of isolation technologies have been proposed such as LOCOS (LOCal Oxidation of Silicon), shallow trench isolation (STI) and so on. The most widely used method for generating the isolation is the LOCOS structure. The LOCOS involves the formation of Field OXides (FOX) in the nonactive regions of the substrate. As device geometry reaches submicron size, conventional LOCOS isolation has a limitation. For example, the bird's beaks structure and shape causes unacceptably large encroachment of the field oxide into the device active regions. Further, the planarity of the surface topography is inadequate for submicron lithography needs. Therefore, trench isolation is one of the newer approaches adopted.
Trench isolation is used primarily for isolating devices in VLSI and ULSI, and hence they can be considered as replacement for conventional LOCOS isolation. Further, shallow trench isolation is gaining popularity for quarter-micron technology. In the basic shallow trench isolation (STI) technology, shallow trenches are aniisotropically etched into the silicon substrate. Next, a CVD oxide is deposited onto the substrate and is then be planarization by CMP (Chemical Mechanical Polishing) or etching back. Another way of the technology is called a Buried OXide with Etch-Stop process (BOXES). The process uses a silicon-nitride etch-stop layer and a pad layer formed on the substrate before the CVD-oxide is deposited.
Unfortunately, the planarization of shallow trench isolation relies on chemical mechanical polishing (CMP) which has been proven an effective but challenging process. As shown in FIG. 1, on a silicon substrate 1, the challenges associated with CMP for STI include dishing 3 of wide trench, erosion of small nitride, and oxide remaining on large nitride. The dishing degrades the planarity of a layer, and it also impacts the control of implantation. The area denoted by 2 is used for isolated device, silicon nitride may be erode the area, completely. This will damage the Si substrate and devices that are fabricated here. The oxide 4 that remains on the silicon nitride layer makes wet strip of silicon nitride unlikely.
The conventional method to solve above described problems will be described as followed. Turning to FIG. 2, a silicon oxide layer 5 is formed on a substrate 1 for using as a pad layer. The thickness of the silicon oxide layer 5 is about 50-150 angstroms. Then, a silicon-nitride layer 7 is deposited on the pad layer 5 to have a thickness about 500-2000 angstroms.
Still turning to FIG. 2, a photoresist is patterned on the silicon-nitride layer 7 to define nonactive regions. Then, shallow trenches are created by using dry etching. The photoresist is subsequently stripped away while the shallow trenches are formed.
Referring to FIG. 3, a silicon oxide layer 9 is deposited on the silicon-nitride layer 7 and is refilled into the shallow trenches for using as an isolation. Generally speaking, the thickness of the silicon oxide layer 9 is about 5000 to 10000 angstroms. Then, a photoresist 11 is pattern exact over the trenches on the silicon oxide layer 9.
Turning to FIG. 4, a dry etching is used to etch a portion of the silicon oxide layer 9 using the photoresist 11 as an etching mask. Then, the photoresist 11 is removed away. A plurality of protruded portions 9a of the silicon oxide layer 9 are generated after the etching. The protruded portions 9a can eliminate the dishing problem. It is because that the removing rate of the CMP performed over the trench is faster than the neighboring regions. Then, a chemical mechanical polishing (CMP) technology is performed for planarization to the surface of the silicon nitride layer 7.
By using the conventional method can improve the result of the CMP planarization. However, the conventional method needs a photomasking step, an etching process and a step to remove the photomasking. The throughput will decrease by using the conventional method. Therefore, no additional mask method is need for polishing trench oxide.